Design of network port surge protection solution

In view of the surge protection requirements of the client network port (such as IEC 61000-4-5 standard), the following multi-level protection device combination is recommended to ensure that the surge test is passed and the back-end circuit is protected.

01  Core protection devices and their functions

02   Typical circuit design (taking RJ45 network port as an example)

Level 1 protection (GDT):
Connect a GDT in parallel between each pair of differential lines (such as TX+/TX-) and the ground to absorb lightning or EFT energy. Selection requirements: DC breakdown voltage ≥90V, current carrying capacity ≥5kA (8/20μs).

Secondary protection (TVS):
Use an integrated TVS array (such as RClamp0524P) to protect four pairs of differential lines, with a clamping voltage of ≤15V and a response time of <1ns to ensure that the residual voltage does not damage the PHY chip.

Common Mode Filtering (羧甲基纤维素钠):
Suppresses common mode noise caused by surges and improves signal integrity.

PoE Power Protection (PTC):
If PoE power supply is supported, connect a PTC in series in the power path to limit overcurrent.

Key Design Considerations

01 PCB layout optimization

The GDT/TVS should be as close to the network port as possible, with short and straight wiring to reduce parasitic inductance; the ground plane should be complete, and multi-point grounding should be used to reduce impedance.

02 Test Standard Match

Contact discharge: ±8kV (IEC 61000-4-2) requires TVS+CMC combination;
Surge test: ±4kV (IEC 61000-4-5) requires GDT+TVS two-level protection.

03 Device Selection Verification

Verify the TVS clamping characteristics through TLP testing; monitor the voltage on the PHY chip pin during actual surge to ensure that it is lower than the withstand voltage (e.g., a 3.3V PHY chip requires a residual voltage of <6V).

03 Recommended solution performance indicators

04 Costs and Alternatives

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