Ethernet PHY Chip Technology White Paper
Global market size
2023: about US$1.2 billion (data source: Yole Développement) 2028 forecast: more than US$2.5 billion (CAGR 15.8%) Growth drivers: data center upgrade (400G/800G PHY demand) automotive intelligence (the number of PHYs per vehicle increased from 1-2 到 10+) Industry 4.0 (industrial Ethernet penetration rate exceeds 50%)
Regional market distribution
North America: 40% (driven by data centers and automotive electronics) Asia Pacific: 35% (China is the main growth pole, 5G base stations and electric vehicles demand) Europe: 20% (Industrial 4.0 and automotive industry chain mature)
Market competition pattern
North America: 40% (driven by data centers and automotive electronics) Asia Pacific: 35% (China is the main growth pole, 5G base stations and electric vehicles demand) Europe: 20% (Industrial 4.0 and automotive industry chain mature)
Future trends
1. Technology direction:
ultra-high speed: 800G PHY (PAM4 modulation, silicon photonics integration) Low power consumption: 3nm process PHY chip (power consumption reduced by 50%) Automotive grade: 10G PHY supports L4/L5 autonomous driving (mass production in 2025)
2. Supply chain changes:
The United States restricts the export of high-end PHY to China, accelerating the process of domestic substitution. TSMC/Samsung are deploying 3nm PHY foundry to compete for the high-end market.
PRODUCT FEATURES
Connect MAC and physical media (copper cable/optical fiber) to ensure stable network transmission
1. Signal conditioning
Convert the parallel data sent by the MAC layer into a serial bit stream, and sample and decode the received analog signal to restore it to a digital signal;
2. Data encoding/decoding
Compensate for the attenuation of high-frequency signals in long-distance cables, eliminate inter-symbol interference (ISI), and restore the signal waveform;
3. Physical media interface
Twisted pair + optical fiber + backplane; built-in ESD protection and common mode suppression;
4. Power management and diagnosis
Close unused transceiver channels when idle, and power consumption can be reduced by 70% in low-power mode; It has the function of detecting cable open circuit/short circuit/impedance abnormality and reading link status;
5. Link negotiation Adapt to the rate
Negotiate the optimal rate (10/100/1000Mbps) with the peer device through FLP (Fast Link Pulse) and quickly establish a reconnection;
Signal conditioning/data encoding and decoding
1. Necessity of signal conditioning
·Signal amplitude adjustment: signal amplification for easy collection;·Improve signal-to-noise ratio: remove noise interference of electrical signals;·Signal conversion: realize signal conversion through functional relationship, which is convenient for observing required parameters;·Meet equipment requirements: signal matching;·Achieve long-distance transmission: anti-interference during long-distance transmission;·Protect equipment: protect back-end equipment when measuring high-voltage signals;
2. Signal conditioning process (applicable to most long-distance communications)
Signal amplification -> Filtering -> Signal conversion -> Linearization -> Isolation protection -> Modulation and demodulation -> Level adjustment;
STRUCTURE DIAGRAM
PHY chip
The PHY (Physical Layer) chip is the core component of the physical layer, responsible for sending and receiving Ethernet signals. The main functions include:
• Signal conversion: convert digital signals into analog signals suitable for network cable transmission (transmission), and convert analog signals into digital signals (reception).
• Electrical protection: provide additional electrical isolation through the network transformer to protect the PHY chip from damage by external factors such as lightning strikes and electromagnetic interference.
Network transformer
• Signal coupling and transmission: enhance and transmit the differential signal output by the PHY chip to the other end of the network cable through differential mode coupling.
• Electrical isolation: isolate the DC level difference between the PHY chip and the network cable to prevent the voltage difference between different devices from damaging the device.
• Impedance matching: ensure impedance matching between the signal source, load and transmission line to reduce signal reflection and bit error.
• Electromagnetic interference suppression: suppress common mode noise and reduce electromagnetic interference through common mode choke (羧甲基纤维素钠).
The above three parts are not necessarily all independent chips. There are mainly the following situations: MAC and PHY are integrated inside the CPU, which is more difficult; MAC is integrated inside the CPU, and PHY uses independent chips (mainstream solution); MAC and PHY are not integrated in the CPU, and MAC and PHY use independent chips or integrated chips (high-end use);
PARAMETERS
1. Rate support
• Supported rate range: The PHY chip needs to support the Ethernet rate required by the target application, such as 10 Mbps, 100 Mbps, 1 Gbps, 10 Gbps, ETC。;
• Adaptive rate negotiation: Support auto-negotiation function, which can automatically select the best rate (such as 10/100/1000 Mbps) and duplex mode (full-duplex/half-duplex) according to the capabilities of the peer device.
2. Interface standard
The PHY chip needs to be compatible with the upper MAC layer. Common interfaces include:
• MII: Applicable to 10/100 Mbps Ethernet.
• RMII: Simplified version of MII with fewer pins, suitable for 10/100 Mbps.
• GMII: Supports 1 Gbps rate.
• RGMII: Simplified version of GMII with fewer pins, suitable for 1 Gbps.
• SGMII: Serial interface, suitable for 1 Gbps with fewer pins.
• Physical medium interface (MDI): supported physical medium types, such as twisted pair (BASE-T), fiber (BASE-X), single twisted pair (BASE-T1), ETC.
3. Transmission distance
• Transmission distance: select a PHY chip that supports the required transmission distance according to application requirements. 例如, 1000BASE-T (Gigabit Ethernet) supports twisted pair transmission up to 100 meters, while fiber PHY (such as 1000BASE-LX) can support longer distances.
4. Power consumption
• Power consumption level: low power design is critical for energy saving and heat management, especially in high-density devices (such as switches) and mobile devices. 例如, a PHY chip that supports the EEE (Energy Efficient Ethernet) standard can reduce power consumption when idle.
• Thermal design: consider the heat dissipation requirements of the PHY chip, especially in high-temperature environments or high-density applications.
5. Reliability and stability
• Electrical isolation: electrical isolation is achieved through a network transformer to protect the PHY chip from damage by external factors such as lightning strikes and electromagnetic interference.
• Anti-interference capability: PHY chips should have good electromagnetic compatibility (EMC) and be able to withstand electromagnetic interference in industrial environments. 例如, they should comply with standards such as CISPR 32 and IEC 61000-4-2.
• Operating temperature range: Industrial-grade PHY chips usually support a wide temperature range (such as -40°C85°C) to adapt to harsh environments.
6. Special functions
• PoE support: If the application needs to be powered by Ethernet cable (such as IP cameras, wireless access points), you need to choose a chip that supports PoE (IEEE 80
• Diagnostic function: Supports functions such as link status detection and signal quality monitoring to facilitate network maintenance and troubleshooting. • Security features: In some applications, PHY chips may need to support security features, such as encrypted communication or authentication functions.
APPLICATION SCENARIO
(1) 10/100Mbps PHY
Application scenarios: Industrial control: PLC, sensor network (such as Modbus TCP) Smart home: smart socket, low-power IoT device (such as Zigbee gateway) On-board diagnostics: OBD-II interface (100BASE-T1)
(2) 1Gbps PHY
Application scenarios: Consumer electronics: 4K TV, NAS storage Industrial camera: machine vision (real-time image transmission) Enterprise network: Gigabit switch, router
(3) 2.5G/5G PHY (Multi-Gigabit)
Application scenarios: Industrial control: PLC, sensor network (such as Modbus TCP) Smart home: smart socket, low-power IoT device (such as Zigbee gateway) On-board diagnostics: OBD-II interface (100BASE-T1)
(4) 10G/25G PHY
Application scenarios: Data center: server interconnection (SFP+/QSFP28) 5G base station: fronthaul network (eCPRI over 25G) Ultra-high-definition video production: 8K video real-time transmission
(5) 40G/100G and above PHY
Application scenarios: AI/supercomputing clusters: GPU/TPU interconnection (InfiniBand replacement) Core backbone network: metropolitan area network/inter-data center interconnection Optical communication: CPRI/OBSAI fiber fronthaul
DESIGN CHOICES
(1) MII (Media Independent Interface)
Rate: 10/100Mbps Number of pins: 16+ Application scenarios: Early embedded systems (such as ARM9 industrial control boards) Low-complexity design (external MAC controller required) Disadvantages: Complex wiring, gradually replaced by RMII
(2) RMII (Reduced MII)
Rate: 10/100Mbps Number of pins: 6 (data + clock) Application scenarios: Cost-sensitive devices (such as home routers) Space-constrained design (IoT modules) Advantages: Simplified wiring, support 50MHz clock
(3) RGMII (Reduced Gigabit MII)
Rate: 1Gbps Number of pins: 12 (dual-edge sampling) Application scenarios: Gigabit switches, industrial gateways need to be compatible with 100M/1G flexible design Key points: Strict timing control is required (±1ns deviation tolerance)
(4) SGMII (Serial Gigabit MII)
Rate: 1G/2.5GbpsNumber of pins: 2 (differential pairs)Application scenarios: long-distance board-to-board connection (via SerDes)High-speed communication between FPGA and PHYAdvantages: strong anti-interference, support backplane transmission
(5) USXGMII (Ultra Speed MII)
Rate: 10GbpsNumber of pins: 4 (differential pairs)Application scenarios: multi-rate switch (10M/100M/1G/10G adaptive)Data center leaf-spine architectureFeatures: low jitter clock required (<0.5ps RMS)
ADVANTAGES
Appropriate reliability strategies can be customized on demand
The reliability test of the product strictly complies with the following international standards:
AEC (Automotive Electronics Council)
JEDEC (Joint Electron Device Engineering Council)
MIL (Military Standard)
IEC (International Electro technical Commission)
To fully ensure product quality, we ensure product reliability from the following five aspects:
Process reliability
Packaging process reliability
Product reliability
Mass production reliability monitoring
Failure analysis
